Hierarchical Process Simulation for Nano‐Electronics | Zendy

R.W. Dutton | Zendy; Edwin C. Kan | Zendy

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Hierarchical Process Simulation for Nano‐Electronics

Author(s) -

R.W. Dutton,

Edwin C. Kan

Publication year - 1998

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/1998/19402

Subject(s) - electronics , key (lock) , process (computing) , point (geometry) , interconnection , computer science , software , scaling , engineering , electronic engineering , computational science , systems engineering , electrical engineering , telecommunications , mathematics , geometry , computer security , programming language , operating system

The challenges of computational electronics are considered from the perspective of processsimulation. Essential limitations for device scaling posed from a technology point of view arediscussed along with many new research opportunities. The key areas considered include:bulk processing, interconnect technology and software engineering for computational electronics

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