Datapath Optimization Using Layout Information: An Empirical Study
Author(s) -
Allen C.-H. Wu
Publication year - 1993
Publication title -
vlsi design
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.123
H-Index - 24
eISSN - 1065-514X
pISSN - 1026-7123
DOI - 10.1155/1997/85473
Subject(s) - datapath , computer science , fidelity , high level synthesis , quality (philosophy) , high fidelity , simple (philosophy) , computer architecture , computer engineering , reliability engineering , parallel computing , embedded system , engineering , telecommunications , philosophy , epistemology , field programmable gate array , electrical engineering
Most datapath synthesis approaches use a simple area model to evaluate design area quality.However, using such a simplified model could mislead synthesis tasks into generating inferiordesigns. This paper presents an extensive experimental study to validate the correlationbetween the tradition area model, our proposed area model, and the actual layouts. Theresults show that traditional area quality measures are not good indicators for optimization indatapath synthesis. Moreover, this paper also shows that to provide accurate indications fordesign tradeoffs in high-level synthesis, the fidelity of the estimates is more important thanthe accuracy
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