Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction

Accurate design descriptions during synthesis allow efficient use of resources. The appropriateuse of distinct implementations of RTL operators helps generate optimal VLSI designs.The system presented here utilizes libraries composed of multiple modules with identicalfunctionality, but distinct performance and area characteristics. Such libraries allow thegeneration of an accurate estimate of the area and delay of the final design during synthesis.Full use of the module selection capability is possible by allowing the user to specify a totalarea limit rather than a detailed allocation. Consequently, tradeoffs between different allocationscan be fully explored. Scheduling, module selection, and allocation are performedsimultaneously to achieve optimal use of area and delay, and to facilitate the incorporation oflower level design considerations into behavioral synthesis. Synthesis decisions are made ina time-constrained and area-constrained fashion, by using both constraints to identify andavoid infeasible design possibilities. Module selection, scheduling, and allocation for pipelineddesigns is also implemented. Experimental results show that the use of module selectionand time-and-area-constrained synthesis results in an area/delay design curve which issuperior to the results of traditional systems