Statistical Module Level Area and Delay Estimation

The increasing complexity of VLSI design process has led to an increasing use of layoutsynthesis systems. For many components of a high-level synthesis system such as modulegenerators and module generator development environments, an accurate model of area anddelay for the layouts generated by a layout synthesis system is extremely desirable. We haveexperimented with a statistical model for area and delay of function modules. This model issurprisingly accurate for a standard cell based layout synthesis systemૼVPNR. The area ofadder and shifter modules can be modeled to with in 5% accuracy while the error in delaymodel is bounded by 4%. This model can be taken through another level of indirectionwithout significant loss in accuracy. The area of all the modules that fit a ripple-template(such as carry-ripple adder) can be modeled with in 30% accuracy. The delay of thesemodules has a better fit, 15%. The square-template designs (such as array multiplier) have anarea model with 1.7% coeificient of variance. In these cases, the model is parametrized bythe area and delay of the leaf cells in the template