Layout Modeling and Design Space Exploration in Pss1 System

This paper presents the design methodology used in PSS1, a high level synthesis systemdesigned for computation dominated applications. It includes a behavior synthesizer and anarea optimizer. Based on a pre-defined architecture, the behavior synthesizer translates adescription into a number of designs with different delays and hardware costs. Based on atwo-level layout model, the area optimizer fine-tunes the physical design using the informationfeedback from the layout tools. All the tools are linked by an X-window interface inwhich users can traverse among different tools and interactively change the design parameters.The output is linked to Lager system [7], a silicon assembler. The layout model allowsa designer to interactively merge/split modules, change the shape of modules, and define thepin positions of modules. Experiments show that a considerable area improvement has beenachieved using this methodology