Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits

Traditionally logic synthesis and layout tools optimize designs without interaction betweenthem. Lack of communication between the two tools often results in inferior post-layoutcircuit implementations. This paper presents three aspects of coupling synthesis with layoutto minimize post-layout area and delay of circuits. It presents two new techniques for computingnet-weights based on timing slacks, and shows how performance improvement withlittle overhead in area can be achieved. Secondly, it presents a novel idea of exploiting logicequivalence information in circuits to minimize circuit area and delay during layout. Analgorithm for computing logic equivalence classes and performing net swapping using theequivalence classes during layout is described. Lastly, it shows the sensitivity of post-layoutdelays of circuits to wiring models used in synthesis and demonstrates how resynthesistechniques can be effectively used to generate good post-layout implementation. Significantreductions in post-layout area and delay on several industrial designs have been observed