Integration of SPICE with TEK LV500 ASIC Design Verification System | Zendy

Ashok Srivastava | Zendy; S. R. Palavali | Zendy

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Integration of SPICE with TEK LV500 ASIC Design Verification System

Author(s) -

Ashok Srivastava,

S. R. Palavali

Publication year - 1994

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/1996/48310

Subject(s) - spice , computer science , interface (matter) , very large scale integration , application specific integrated circuit , unix , software , graphical user interface , embedded system , computer hardware , computer architecture , electronic engineering , operating system , engineering , bubble , maximum bubble pressure method

The present work involves integration of the simulation stage of design of a VLSI circuit and its testing stage. The SPICE simulator, TEK LV500 ASIC Design Verification System, and TekWaves, a test program generator for LV500, were integrated. A software interface in ‘C’ language in UNIX ‘solaris 1.x’ environment has been developed between SPICE and the testing tools (TekWAVES and LV500). The function of the software interface developed is multifold. It takes input from either SPICE2G.6 or SPICE 3e.1. The output generated by the interface software can be given as an input to either TekWAVES or LV500. A graphical user interface has also been developed with OPENWlNDOWS using Xview tool kit on SUN workstation. As an example, a two phase clock generator circuit has been considered and usefulness of the software demonstrated. The interface software could be easily linked with VLSI design such as MAGIC layout editor

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