Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays | Zendy

Stephen D. Brown | Zendy; Muhammad Khellah | Zendy; Guy Lemieux | Zendy

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Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays

Author(s) -

Stephen D. Brown,

Muhammad Khellah,

Guy Lemieux

Publication year - 1996

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/1996/45983

Subject(s) - router , routing (electronic design automation) , field programmable gate array , benchmark (surveying) , computer science , electronic circuit , static routing , embedded system , parallel computing , engineering , computer network , routing protocol , electrical engineering , geodesy , geography

This paper addresses several issues involved for routing in Field-Programmable Gate Arrays (FPGAs) that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A two-stage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing. We present a new detailed routing algorithm designed specifically for the types of routing structures found in the most recent generation of FPGAs, and show that the new algorithm achieves significantly better results than previously published FPGA routers with respect to the speed-performance of implemented circuits

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