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Generation of test plans is a crucial step for testing VLSI circuits. This paper presents a modified approach to test plan generation for the BILBO test methodology. A few limitations of the existing approaches have been identified and methods to address these have been suggested. The proposed approach has been implemented for the general case of n-port combinational logic blocks (CLBs). However, due to limitations of space and for clarity,only 2-port CLBs are considered in this paper. For this case, the problem is modelled as a Step Scheduling Matrix and an algorithm is presented for the solution. The algorithm has been tested on a number of benchmark circuits and the results are compared with those obtained through existing methods. The effectiveness of the proposed approach is clear from the results, as it contributes to the reduction in total testing time as well as generates a largernumber of test plans

A Modified Approach to Test Plan Generation for Combinational Logic Blocks