A Novel Path Delay Fault Simulator Using Binary Logic | Zendy

Ananta K. Majhi | Zendy; James Jacob | Zendy; L.M. Patnaik | Zendy

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A Novel Path Delay Fault Simulator Using Binary Logic

Author(s) -

Ananta K. Majhi,

James Jacob,

L.M. Patnaik

Publication year - 1996

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/1996/25839

Subject(s) - benchmark (surveying) , fault simulator , algorithm , binary number , path (computing) , combinational logic , fault (geology) , sequential logic , computer science , logic simulation , logic gate , electronic circuit , computer engineering , mathematics , fault detection and isolation , stuck at fault , arithmetic , engineering , artificial intelligence , geodesy , seismology , geology , actuator , programming language , geography , electrical engineering

A novel path delay fault simulator for combinational logic circuits which is capable of detecting both robust and nonrobust paths is presented. Particular emphasis has been given for the use of binary logic rather than the multiple-valued logic as used in the existing simulators which contributes to the reduction of the overall complexity of the algorithm. A rule based approach has been developed which identifies all robust and nonrobust paths tested by a two-pattern test , while backtracing from the POs to PIs in a depth-first manner. Rules are also given to find probable glitches and to determine how they propagate through the circuit, which enables the identification of nonrobust paths. Experimental results on several ISCAS'85 benchmark circuits demonstrate the efficiency of the algorithm

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