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This paper investigates the possibility of using Field-Programmable Gate Arrays (Fr’GAS) as\udreconfigurable co-processors for workstations to produce moderate speedups for most tasks\udin the design process, resulting in a worthwhile overall design process speedup at low cost\udand allowing algorithm upgrades with no hardware modification. The use of FPGAS as hardware\udaccelerators is reviewed and then achievable speedups are predicted for logic simulation\udand VLSI design rule checking tasks for various FPGA co-processor arrangements

The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks