The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks | Zendy

N. Howard | Zendy; Andrew M. Tyrrell | Zendy; N.M. Allinson | Zendy

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The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks

Author(s) -

N. Howard,

Andrew M. Tyrrell,

N.M. Allinson

Publication year - 1996

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/1996/17505

Subject(s) - field programmable gate array , speedup , computer science , workstation , process (computing) , very large scale integration , computer architecture , electronic design automation , hardware acceleration , automation , embedded system , acceleration , gate array , programmable array logic , logic synthesis , reconfigurable computing , computer hardware , parallel computing , logic gate , engineering , logic family , operating system , algorithm , mechanical engineering , physics , classical mechanics

This paper investigates the possibility of using Field-Programmable Gate Arrays (Fr’GAS) as\udreconfigurable co-processors for workstations to produce moderate speedups for most tasks\udin the design process, resulting in a worthwhile overall design process speedup at low cost\udand allowing algorithm upgrades with no hardware modification. The use of FPGAS as hardware\udaccelerators is reviewed and then achievable speedups are predicted for logic simulation\udand VLSI design rule checking tasks for various FPGA co-processor arrangements

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