A General Approach to Boolean FunctionDecomposition and its Application in FPGABasedSynthesis

An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in thispaper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representationof the function by a set of r-partitions over the set of minterms. Two different decomposition strategies, namely serial andparallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completelyor incompletely specified, single- or multiple-output functions and is suitable for different types of FPGAs includingXILINX, ACTEL and ALGOTRONIX devices. The results of the benchmark experiments presented in the paper show that,in several cases, our method produces circuits of significantly reduced complexity compared to the solutions reported in the literature