Designing Interconnection Networks for Multi-level Packaging
Author(s) -
M.T. Raghunath,
Abhiram Ranade
Publication year - 1995
Publication title -
vlsi design
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.123
H-Index - 24
eISSN - 1065-514X
pISSN - 1026-7123
DOI - 10.1155/1995/57617
Subject(s) - interconnection , computer science , distributed computing , hierarchy , set (abstract data type) , bandwidth (computing) , multithreading , topology (electrical circuits) , computer architecture , computer network , engineering , thread (computing) , electrical engineering , operating system , economics , market economy , programming language
A central problem in building large scale parallel machines is the design of the interconnection network. Interconnectionnetwork design is largely constrained by packaging technology. We start with a generic set of packagingrestrictions and evaluate different network organizations under a random traffic model. Our results indicate thatcustomizing the network topology to the packaging constraints is useful. Some of the general principles that ariseout of this study are: 1) Making the networks denser at the lower levels of the packaging hierarchy has a significantpositive impact on global communication performance, 2) It is better to organize a fixed amount of communicationbandwidth as a smaller number of high bandwidth channels, 3) Providing the processors with the ability to toleratelatencies (by using multithreading) is very useful in improving performance
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