A Comparative Study of Synchronous Clocking Schemes for VLSI Based Systems

Recently a novel clock distribution scheme called Branch-and-Combine(BaC) has been proposed. The schemeguarantees constant skew bound irrespective of the size of the clocked network. It utilizes simple nodes to processclock signals such that clock paths are adaptively selected to guarantee constant skew bound. The paper uses aVLSI model to compare the properties of the new scheme to those of the well established H-Tree approach. TheH-Tree is a binary tree of simple buffers which is laid out such that leaves are at equal distances from the root.Our study considers clocking 2-D processor meshes of arbitrary sizes. We evaluate and compare the relevantparameters of both schemes in a VLSI layout context. We utilize parameters such as clock skew, link costs, nodecosts and area efficiency as the basis for comparison. We show that for each BaC network, there is a certainthreshold size after which it outperforms the corresponding tree network in terms of skew. We also show thatexcept for node costs, BaC networks outperform the H-Tree, especially when the size of the clocked network islarge. As an extension we show that BaC clocking does not suffer from potential pulse disappearance, no matterhow large the network is