Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors | Zendy

S. K. Nandy | Zendy; R. Panwar | Zendy

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Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors

Author(s) -

S. K. Nandy,

R. Panwar

Publication year - 1990

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/1994/96830

Subject(s) - very large scale integration , speedup , computer science , representation (politics) , parallel computing , quadtree , algorithm , cad , engineering drawing , engineering , embedded system , politics , political science , law

Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC) of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors

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