High Throughput Error Control Using Parallel CRC | Zendy

A. Sobski | Zendy; A. Albicki | Zendy

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High Throughput Error Control Using Parallel CRC

Author(s) -

A. Sobski,

A. Albicki

Publication year - 1993

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/1994/90841

Subject(s) - encoder , computer science , shift register , throughput , detector , error detection and correction , algorithm , simple (philosophy) , basis (linear algebra) , parallel computing , computer hardware , mathematics , telecommunications , chip , philosophy , geometry , epistemology , wireless , operating system

Redesigning the LFSR (Linear Feedback Shift Register) so that syndrome calculations can be performed in onesweep allows for fast error control in high speed computer networks. The resulting structure forms the basis ofthe PEDDC (Parallel Encoder, Decoder, Detector, Corrector) which replaces the conventional Serial Encoder,Decoder, Detector, Corrector for generation and utilization of cyclic codes. Since syndromes are calculated inas little as one clock period, information from which the syndrome is calculated can be processed in a parallelstream. In this paper a simple PEDDC is built, its operation is examined in detail, its performance is comparedwith a serial counterpart, possible variations on the PEDDC structure is given, and further speed enhancementtechniques are considered

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