Execution of VHDL Models Using Parallel Discrete Event Simulation Algorithms

In this paper, we discuss the use of parallel discrete event simulation (PDES) algorithms for execution of hardwaremodels written in VHDL. We survey central event queue, conservative distributed and optimistic distributedPDES algorithms, and discuss aspects of the semantics of VHDL and VHDL-92 that affect the use of thesealgorithms in a VHDL simulator. Next, we describe an experiment performed as part of the Vsim Project at theUniversity of Adelaide, in which a simulation kernel using the central event queue algorithm was developed. Wepresent measurements taken from this kernel simulating some benchmark models. It appears that this technique,which is relatively simple to implement, is suitable for use on small scale multiprocessors (such as current desktopmultiprocessor workstations), simulating behavioral and register transfer level models. However, the degree ofuseful parallelism achievable on gate level models with this technique appears to be limited