Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits | Zendy

M.O. Esonu | Zendy; D. Al-Khalili | Zendy; C. Rozon | Zendy

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Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits

Author(s) -

M.O. Esonu,

D. Al-Khalili,

C. Rozon

Publication year - 1994

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/1994/70696

Subject(s) - cmos , bicmos , testability , emitter coupled logic , logic gate , electronic engineering , fault (geology) , stuck at fault , computer science , digital electronics , fault model , engineering , electronic circuit , fault detection and isolation , logic family , electrical engineering , voltage , logic synthesis , reliability engineering , transistor , actuator , seismology , geology

The logic behavior and performance of ECL gates under a set of defect models are examined. These are comparedwith equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaininga sufficiently high fault coverage, e.g., 79% for ECL versus 54% for BiCMOS and 69% for CMOS equivalentgates. Performance degradation faults such as delay, current and Voltage Transfer Characteristics (VTC) or NoiseMargin (NM) faults are analyzed as applied to these gates. It is shown that logical fault testing with delay faulttesting yields the highest fault coverage for BiCMOS and CMOS gates (around 95%). However, for equivalentECL gates to attain a fault coverage of around 98%, both logical and NM fault testing have to be used

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