Block-Level Logic Extraction from CMOS VLSI Layouts | Zendy

Inderpreet Bhasin | Zendy; Joseph G. Tront | Zendy

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Block-Level Logic Extraction from CMOS VLSI Layouts

Author(s) -

Inderpreet Bhasin,

Joseph G. Tront

Publication year - 1991

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/1994/67035

Subject(s) - extractor , cmos , pass transistor logic , electronic engineering , computer science , block (permutation group theory) , logic gate , logic family , resistor–transistor logic , transistor , very large scale integration , logic optimization , electrical engineering , logic synthesis , engineering , electronic circuit , digital electronics , mathematics , geometry , voltage , process engineering

This paper describes a Prolog based Block Extraction System (ProBES) which converts a transistor level descriptionof a CMOS circuit into a logic block level description. The operation of ProBES is conceptually similar to thatof a circuit extractor. However, whereas a circuit extractor is used to identify circuit primitives such as transistors,resistors and capacitors from the geometrical information in a mask level layout description, ProBES can be usedto identify predefined gates and logic blocks in a CMOS transistor network. ProBES operates according to thecircuit hierarchy. Basic gates such as inverters, transmission-gates, nands, nors, etc. are identified first. Logicblocks composed of these gates are then identified. More complex blocks which contain blocks already identifiedare recognized next and so on. ProBES is meant to be used as an aid in the verification of logic design. It canprovide a connectivity check for a circuit

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