Technology Mapping for FPGA Using Generalized Functional Decomposition | Zendy

KuoHua Wang | Zendy; Cheng Chen | Zendy; Ting Ting Hwang | Zendy

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Technology Mapping for FPGA Using Generalized Functional Decomposition

Author(s) -

KuoHua Wang,

Cheng Chen,

Ting Ting Hwang

Publication year - 1994

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/1994/56371

Subject(s) - functional decomposition , partition (number theory) , decomposition , field programmable gate array , computer science , set (abstract data type) , dependency (uml) , encoding (memory) , function (biology) , algorithm , variable (mathematics) , theoretical computer science , mathematics , artificial intelligence , embedded system , machine learning , combinatorics , ecology , mathematical analysis , evolutionary biology , programming language , biology

In this paper, we address the technology mapping for RAM-based FPGA. Functional decomposition is appliedto decompose a large function into a set of smaller subfunctions such that each subfunction can be implementedusing a single logic cell. Our system is mainly divided into two parts. The first part is designed specifically fortotally symmetric functions. A Fast-Decompose algorithm based on weight dependency is proposed. The secondpart deals with general functions. We consider some techniques such as output partition, variable partition, don'tcare assignment and encoding to minimize the number of subfunctions derived. Using these techniques together,our tool, Fun-Map, improves the mapping results compared with other tools in terms of area and delay

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