Register-Transfer Synthesis of Pipelined Data Paths

We present a new approach to the problem of register-transfer level design optimization of pipelined data paths.The output of high level synthesis procedures, such as Sehwa, consists of a schedule of operations into time steps,and a fixed set of hardware operators. In order to obtain a register-transfer level design, we must assign operationsto specific operators, values to registers, and finish the interconnections. We first perform module assignmentwith the goal of minimizing the interconnect requirements between RT-level components as a preprocessingprocedure to the RT-level design. This will result in a smaller netlist which makes the design more compact andthe design process more efficient. In addition to reducing the total number of interconnects, this approach willalso reduce the total number of multiplexors in the design by eliminating unnecessary multiplexing at the inputsof shared modules. The interconnect sharing task is modeled as a constrained clique partitioning problem. Wedeveloped a fast and efficient polynomial time heuristic procedure to solve this problem. This procedure is 30–50 times faster than other existing heuristics while still producing better results for our purposes. Using thisprocedure, we can produce near optimal interconnect sharing schemes in a few seconds for most practical sizepipelined designs. This efficient approach will enable designers to explore a larger portion of the design spaceand trade off various design parameters effectively