An Improved Data Flow Architecture for Logic Simulation Acceleration

The high degree of parallelism in the simulation of digital VLSI systems can be utilized by a data flow architectureto reduce the enormous simulation times. The existing logic simulation accelerators based on the data flow principleuse a static data flow architecture along with a timing wheel mechanism to implement the event driven simulationalgorithm. The drawback in this approach is that the timing wheel becomes a bottleneck to high simulationthroughput. Other shortcomings of the existing architecture are the high communication overhead in the arbitrationand distribution networks, and reduced pipelining due to a static data flow architecture. To overcome these, threemajor improvements are made to the design of a classical data flow based logic simulation accelerator. Theseinclude