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We present a design method (called STD architecture) to design large memories so that the test time does notincrease with the increasing size of memory. Large memories can be constructed by using several small blocksof memory. The memory address decoder is divided into two or more levels and designed such that during thetest mode all small memory blocks are accessed together. With the help of modified decoder, all small memoryblocks are tested in parallel using any standard test algorithm. In this design, time to test the whole memory isequal to the time required to test one small block. The proposed design is highly structured and hardware overheadis negligible. The basic idea is to exploit internal hardware for testing purpose. With the proposed method aconstant test time can be achieved irrespective of the memory size. STD architecture is applicable to memorychips as well as memory boards, and the design is suitable for fault detection as well as for fault diagnosis

STD Architecture: A Practical Approach to Test M-Bits Random Access Memories