Resolution Enhancement in IDDQ Testing for Large ICs | Zendy

Yashwant K. Malaiya | Zendy; Anura P. Jayasumana | Zendy; C.Q. Tong | Zendy; S.M. Me | Zendy

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Resolution Enhancement in I_DDQ Testing for Large ICs

Author(s) -

Yashwant K. Malaiya,

Anura P. Jayasumana,

C.Q. Tong,

S.M. Me

Publication year - 1994

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/1994/27973

Subject(s) - iddq testing , cmos , very large scale integration , integrated circuit , electronic engineering , reliability engineering , power (physics) , computer science , engineering , electrical engineering , physics , quantum mechanics

Current drawn by a static CMOS VLSI integrated circuit during quiescent periods is extremely small and isnormally of the order of nanoamperes. However, it is remarkably susceptible to a number of failure modes. Manyfaults present in such ICs cause the quiescent power-supply current (IDDQ) to increase by several orders ofmagnitude. Some of these faults may not manifest themselves as logical faults, and would not be detected bytraditional IC test techniques

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