Coverage of Node Shorts Using Internal Access and Equivalence Classes

A method is presented that determines the coverage of shorts (bridging failures) in digital logic circuits by internalaccess test techniques. These are test techniques that provide observability of circuit nodes, such as CMOS powersupply current monitoring (including IDDQ), CrossCheck, and voltage contrast. Only fault-free circuit simulationis used to obtain node states. Two versions of the algorithm are presented: a simple algorithm that is suitable foruse with two-state logic (0 and 1), and a more general algorithm for four-state logic (0, 1, X, and Z). The resultis a set of sets of nodes, where a list of all potential shorts that could exist in the circuit yet be undetected aftertesting is obtained easily from the power sets of these sets; unlike other approaches the full universe of potentialshorts is not generated. Experiments show that short, randomly generated sequences of test vectors detectessentially all detectable shorts of multiplicity 2 for both combinational and sequential circuits