Theory, Analysis and Implementation of an On-Line BIST Technique

A Built-ln Concurrent Self-Test (BICST) technique for testing combinational logic circuits concurrently with theirnormal operation is proposed. Concept of sharing the test hardware between identical circuits to reduce theoverall area overhead is introduced. The method was implemented in the design of an ALU with on-line testcapability in CMOS technology. The additional hardware used for a 12-bit ALU was 19% of the total chip areaand it did not impose any timing overhead on the operation of the ALU. The overhead decreases with an increasein the size of the ALU