Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits | Zendy

K. Z. Dimopoulos | Zendy; J.N. Avaritsiotis | Zendy; S. J. White | Zendy

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Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits

Author(s) -

K. Z. Dimopoulos,

J.N. Avaritsiotis,

S. J. White

Publication year - 1991

Publication title -

active and passive electronic components

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.144

H-Index - 22

eISSN - 1026-7034

pISSN - 0882-7516

DOI - 10.1155/1992/13545

Subject(s) - inductance , capacitance , interconnection , lossy compression , chip , electronic circuit , electronic engineering , integrated circuit , lcr meter , nonlinear system , transmission line , electric power transmission , voltage , electrical engineering , engineering , computer science , physics , telecommunications , electrode , quantum mechanics , artificial intelligence

A method for the electrical parameters analysis and modelling of lossy-coupled multilayer on-chipinterconnection lines at high bit rates is presented in detail. It can be used by the VLSI designer toanalyze on-chip interconnections with linear, as well as nonlinear/time varying terminators and tosimulate the pulse propagation characteristics in high-speed integrated circuits. First the capacitance,inductance, conductance and resistance matrices per unit length for the given multiconductor geometryis computed. A multiple coupled line model consisting of uncoupled lossy transmission lines and lineardependent current and voltage sources if finally calculated according to the capacitance, inductance,conductance and resistance matrix values computed

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