Design and Fabrication of SOI Field-Effect-Diode Memory Cells

Memory arrays consume a very large area in chip designs; yet memory cell scaling lags significantly transistor scaling. With transistor channel lengths in the nanoscale regime, the six transistor static random access memory cell (6T-SRAM) and the single transistor dynamic memory (DRAM) cell both suffer from excessive leakage current. Consequently, there is a widely recognized need for urgent progress in memory technology. The Thin Capacitively Coupled Thyristor (TCCT) based memory cell (T-RAM) approach is a most promising, CMOS compatible alternative to the “standard” cell both for SRAM [1] and DRAM cell [2] designs. However, the T-RAMs demand the precise control of doping profiles of the p-n junctions involved in order to achieve correct breakdown characteristics. To address this difficulty, we explore here, the possibility of replacing the thyristor with a suitable Field Effect Diode (FED). The FED displays I-V characteristics similar to those of the TCCT, without suffering from the above technological drawback [3][4] and is essentially an augmented I-MOS transistor [5][6], to which a second gate has been added. Through numerical simulations, a thorough investigation is carried out of the effects of the gate work function, and of varying the device dimensions, including the length of the two gates and the width of the gap between them, as well as the substrate Silicon-on-Insulator (SOI) layer thickness. On the basis of our results, the scalability and performance of the FED and TCCT structures and their potentials for memory applications are compared: it is found that the FED is the preferred choice for memory applications. Experimental results supporting some of the above conclusions will also be presented at the meeting, obtained from “relaxed” geometry Si-nanowire based FED memory cells.