Open AccessProcess Engineering and Trap Distribution for Dielectric/Si Interfacial Layer in High-k Gated MOS Devices
Author(s) -
KueiShu ChangLiao,
Chung-Hao Fu,
Chun-Chang Lu,
Yu-An Chang,
Ya-Yin Hsu,
TienKo Wang,
Dawei Heh
Publication year - 2011
Publication title -
meeting abstracts/meeting abstracts (electrochemical society. cd-rom)
Language(s) - English
Resource type - Journals
eISSN - 2151-2035
pISSN - 1091-8213
DOI - 10.1149/ma2011-01/22/1343
Subject(s) - trap (plumbing) , materials science , layer (electronics) , dielectric , process (computing) , optoelectronics , engineering physics , distribution (mathematics) , high κ dielectric , nanotechnology , computer science , engineering , operating system , environmental engineering , mathematical analysis , mathematics
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