High k Dielectrics on High-Mobility Substrates: The Interface!

The down-scaling trend of complementary metal oxide semiconductor (CMOS) field effect transistor (FET) will continue as it decreases the cost per function in a chip, decreases power consumption, and increases performance. To reduce power consumption from gate oxide leakage, Intel Corporation has successfully introduced high k dielectrics for 45 nm CMOS technology. We have, therefore, come a long way since a feature article on this topic was published in Interface in 2005.1 Many deposition and reliability issues have been resolved on silicon substrate. To further enhance the performance and with recent advancement of high k metal gate technology, the semiconductor industry is again showing interest in high-mobility substrates such as Ge and III-V materials for CMOS technologies.2-5 Direct deposition of high k dielectric somehow reduces the burden of finding a stable oxide such as SiO2 in Si. While Ge is being considered for high hole mobility, III-V materials such as GaAs, InP, InGaAs, InAs, and GaSb are being considered for their high electron mobility. Once these materials are integrated into the MOS device architecture, it will lead to a functional diversification with additional applications like high performance analog/ RF devices. According to the perspective on future evolution of CMOS technologies as presented at the International Technology Roadmap for Semiconductors (ITRS) (2010 edition)6 several critical issues need to be resolved before these channel materials are integrated into the CMOS device/ process technologies. Several recent ECS symposia, “Dielectrics on Nanosystems,”7 “High Dielectric Constant and Other Dielectric Materials for Nanoelectronics and Photonics”8 and “Graphene, Ge/III-V, Nanowires, and Emerging Materials for PostCMOS Applications,”9 have addressed these issues. First, alternate channel materials cointegrated with high k dielectric are required to implement high mobility n and p channels. Because III-V semiconductors have high electron mobility, (but low hole mobility), while germanium conversely has high hole mobility (but low electron mobility), selective growth of alternate channel materials in desired locations with controlled properties and directions on silicon wafers has become necessary. Second, formation of low-resistive source and drain with the allowed thermal budget is also required. Third, the channel structures may be different if the scaled device structures are modified to either FinFETs or nanowire structures. The other critical issue is the growth of high k dielectrics with an unpinned Fermi level in the alternate channel material. This issue schematically outlined in Fig. 1. Electrical performance of the high k/ substrate interface depends on the deposition process, type of high k dielectric, and precise selection of deposition parameters, predeposition surface treatments, and subsequent annealing temperatures. Some types of dielectric materials may not easily nucleate in the same way on every type of substrate. Once the dielectric is deposited it may form a native oxide that could be detrimental to the electrical parameters of the interface. Preand post-deposition treatment may lead to different passivation mechanisms to improve the electrical properties. Unlike silicon, where the interface is well understood, the nature of the unpassivated dangling bonds may vary for various high-mobility substrates. Some of these interface states may be passivated by simple forming gas anneal or nitridation where others may require specialized passivation methods such as a-slicon, germanium or sulfur. Recent initiatives7-9 in this technology area outline the focus of current research to understand the interface states in high mobility substrates. Here some of the interface properties of high-k and the high-mobility channel materials are reviewed for both Ge and various III-V substrates. Interface Electrical Parameters