Silicon CMOS Ohmic Contact Technology for Contacting III-V Compound Materials

Silicon (Si)-encapsulated III-V compound (III-V) device layers enable Si-complementary metal-oxide semiconductor (CMOS) friendly ohmic contact formation to III-V compound devices, allowing for the ultimate seamless planar integration of III-V and Si CMOS devices in a common fabrication infrastructure. A method of making ohmic contacts to buried III-V films using silicide metallurgies has been established. NiSi/Si/III-V dual heterojunction contact structures are found to be optimal for integration. These structures allow contact resistivities to be controlled by Si/III-V interfaces and eliminate interactions between the buried III-V device and metal layers. Using a modified transmission line method (TLM) test structure fabricated using standard CMOS processing techniques, the specific contact resistivities of Si/GaAs and Si/InxGa1-xAs interfaces are extracted. The relationship between specific contact resistivity and heterojuntion barrier width is considered. Among the structures tested in this work, p-type Si/GaAs and n-type Si/InxGa1-xAs yielded the lowest contact resistivities. Using the p-type Si/GaAs interface, a GaAs/AlxGa1-xAs laser with NiSi top contact is demonstrated, confirming the feasibility of NiSi/Si/III-V contact structures for III-V devices.Ratheon Company (Raytheon Integrated Device Systems funding