Open AccessDown-scaling of Thin-Film Transistors: Opportunities and Design Challenges
Author(s) -
Xiaojun Guo,
Radu A. Sporea,
John M. Shan,
S. Ravi P. Silva
Publication year - 2009
Publication title -
ecs transactions
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.235
H-Index - 52
eISSN - 1938-6737
pISSN - 1938-5862
DOI - 10.1149/1.3152980
Subject(s) - materials science , thin film transistor , scaling , transistor , electronics , optoelectronics , substrate (aquarium) , engineering physics , thermal management of electronic devices and systems , thermal conductivity , dissipation , silicon , electronic engineering , electrical engineering , nanotechnology , mechanical engineering , engineering , physics , voltage , composite material , oceanography , geometry , mathematics , layer (electronics) , geology , thermodynamics
With the ever-increasing demands for integration of advanced electronic functions into large-area electronics, down-scaling of thin-film transistors (TFTs) becomes very necessary. The key device operational issues associated with TFT scaling, including short-channel effects (SCEs) and self-heating, are considered in this paper. Device structure engineering approaches are introduced to suppress the SCEs for designing short-channel TFTs with excellent digital and analog performance. And electro-thermal simulation results show that the self-heating in TFTs will be much more significant than that in silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) due to the substrate of poor thermal conductivity. Enhancing the heat dissipation by placement of metal heat pipe in the cap dielectric layers is proved to be an effective way to deal with the heating issues
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