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High-Aspect-Ratio Copper-Via-Filling for Three-Dimensional Chip Stacking
Author(s) -
Kazuo Kondo,
Toshihiro Yonezawa,
Daisuke Mikami,
Toshikazu Okubo,
Yuichi Taguchi,
Kenji Takahashi,
Dale P. Barkey
Publication year - 2005
Publication title -
journal of the electrochemical society
Language(s) - English
Resource type - Journals
eISSN - 1945-7111
pISSN - 0013-4651
DOI - 10.1149/1.2041047
Subject(s) - copper interconnect , interconnection , copper , materials science , chip , aspect ratio (aeronautics) , copper plating , plating (geology) , void (composites) , electrochemistry , electrode , stacking , optoelectronics , composite material , chemical engineering , nanotechnology , chemistry , metallurgy , electroplating , electrical engineering , layer (electronics) , computer science , organic chemistry , engineering , computer network , geophysics , geology

Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced signal delay. Formation of suitable vias by electrodeposition into cavities presents a filling problem similar to that encountered in the damascene process. Because via dimensions for through-chip filling are larger and have a higher aspect ratio relative to features in damascene, process optimization requires modification of existing superconformal plating baths and plating parameters. In this study, copper filling of high-aspect-ratio through-chip vias was investigated and optimized with respect to plating bath composition and applied current wavetrain. Void-free vias 70 mu m deep and 10 mu m wide were formed in 60 min using additives in combination with pulse-reverse current and dissolved-oxygen enrichment. The effects of reverse current and dissolved oxygen on the performance of superfilling additives is discussed in terms of their effects on formation, destruction, and distribution of a Cu(I) thiolate accelerant. (c) 2005 The Electrochemical Society. All rights reserved.

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