A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor

Single-event upsets from particle strikes have become akey challenge in microprocessor design. Techniques todeal with these transient faults exist, but come at a cost.Designers clearly require accurate estimates of processorerror rates to make appropriate cost/reliability trade-offs.This paper describes a method for generating theseestimates.A key aspect of this analysis is that some single-bit faults(such as those occurring in the branch predictor) will notproduce an error in a program's output. We define astructure's architectural vulnerability factor (AVF) as theprobability that a fault in that particular structure willresult in an error. A structure's error rate is the product ofits raw error rate, as determined by process and circuittechnology, and the AVF.Unfortunately, computing AVFs of complex structures,such as the instruction queue, can be quite involved. Weidentify numerous cases, such as prefetches, dynamicallydead code, and wrong-path instructions, in which a faultwill not affect correct execution. We instrument a detailedIA64 processor simulator to map bit-level microarchitecturalstate to these cases, generating per-structure AVFestimates. This analysis shows AVFs of 28% and 9% forthe instruction queue and execution units, respectively,averaged across dynamic sections of the entire CPU2000benchmark suite.