System level memory optimization for hardware-software co-design

Application studies in the areas of image and video processing systems indicate that between 50 and 80% of the area cost in (application-specific) architectures for real-time multi-dimensional signal processing is due to data storage and transfer of array signals. This is true for both single- and multi-processor realizations, both customized and (embedded) programmable targets. This paper has two main contributions. First, to reduce this dominant cost, we propose to address the system-level storage organization for the multi-dimensional signals as a first step in the overall methodology to map these applications, before the HW/SW-partitioning decision. Secondly, we will demonstrate the usefulness of this novel approach based on a realistic test-vehicle, namely a quad-tree based image coding application.