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An instruction timing model of CPU performance
Author(s) -
Bernard L. Peuto,
Leonard J. Shustek
Publication year - 1977
Publication title -
acm sigarch computer architecture news
Language(s) - English
Resource type - Journals
eISSN - 1943-5851
pISSN - 0163-5964
DOI - 10.1145/633615.810667
Subject(s) - computer science , ibm , pipeline (software) , parallel computing , cache , branch predictor , implementation , computer architecture , operating system , compensation (psychology) , cpu cache , superscalar , supercomputer , programming language , psychology , materials science , psychoanalysis , nanotechnology

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