Multiple Instruction Issue And Single-chip Processors

In this paper we evaluate the performance of single-chip processors with multiple functional units. As a basis for our studies we use a processor model that is very similar to many of today's single-chip processors. Using this basic machine model, we investigate the performance that can be achieved if some limited form of multiple instruction issue is supported. For these investigations, we use 4 variants of the basic machine that represented different memory access times and branch execution times. In particular, we evaluate issuing 2 instructions per cycle and find that by restricting multiple instruction issue to load or branch instructions much of the same performance gains can be achieved as in the unrestricted form.