Exploiting VLIW schedule slacks for dynamic and leakage energy reduction

The mobile computing device market is projected to grow 16.8 million units in 2004, representing an average annual rate of 28% over the five year forecast period [5]. This brings the technologies that optimize system energy to forefront. As circuits continue to scale in future, it would important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels.Schedule slacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present compiler-directed techniques that take advantage schedule slacks to optimize leakage and dynamic energy consumption. The proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit level simulation. Our results show that a unified scheme that uses both dynamic and leakage energy reduction techniques is effective in reducing energy consumption.