Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication | Zendy

Takanori Okuma | Zendy; Koji Hashimoto | Zendy; Kazuaki Murakami | Zendy

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Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication

Author(s) -

Takanori Okuma,

Koji Hashimoto,

Kazuaki Murakami

Publication year - 2001

Publication title -

qir (kyushu university institutional repository) (kyushu university)

Language(s) - English

Resource type - Conference proceedings

ISBN - 0-7803-6634-4

DOI - 10.1145/370155.370257

Subject(s) - computer science , dram , data link layer , field programmable gate array , interface (matter) , embedded system , network interface , link (geometry) , data link , computer network , computer architecture , link layer , physical layer , computer hardware , software , operating system , wireless , network packet , bubble , maximum bubble pressure method

We are proposing "PPRAM-Link": a new high-speed communication standard for merged-DRAM/logic SoC architecture. PPRAM-Link standard is composed of physical/logical layers and an API for the upper software layer, which are standardized by PPRAM Consortium. We developed a PPRAM-Link Interface IP family, or "PLIF Core" that realizes logical protocols necessary for subaction-level communications, and it can be applied to various applications. In addition, we designed an FPGA-based PCI-to-PPRAM-Link board for inter-PC/WS communications.

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