Design space exploration of near memory accelerators

We describe an in-progress approach to resolving the opposing goals of speed and accuracy in designing, prototyping, and evaluating the system level performance of near-memory accelerators. Hardware emulators offer high fidelity and speed at the expense of flexibility in exploring the design space. Software simulators can be enormously flexible, but simulation speed suffers if high accuracy is required. Building on past experience of using both these methods, we report on progress with using SystemC simulation for full application level evaluation with eventual synthesis of the accelerator hardware components for emulation.