Extended recursive analysis for tilera tile64 NoC architectures | Zendy

Hamdi Ayed | Zendy; JeanLuc Scharbarg | Zendy; Jérôme Ermont | Zendy; Christian Fraboul | Zendy

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Extended recursive analysis for tilera tile64 NoC architectures

Author(s) -

Hamdi Ayed,

JeanLuc Scharbarg,

Jérôme Ermont,

Christian Fraboul

Publication year - 2017

Publication title -

acm sigbed review

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.27

H-Index - 5

ISSN - 1551-3688

DOI - 10.1145/3166227.3166232

Subject(s) - network on a chip , computer science , network calculus , tree traversal , ethernet , interconnection , avionics , embedded system , focus (optics) , heterogeneous network , computer architecture , parallel computing , computer network , distributed computing , engineering , wireless network , wireless , quality of service , algorithm , telecommunications , physics , optics , aerospace engineering

A heterogeneous network, where a switched-Ethernet backbone, e.g. AFDX, interconnects several end systems based on Network-on-Chip (NoC), is a promising candidate to build new avionics architectures. When using such a heterogeneous network for real-time applications, a global worst-case traversal time (WCTT) analysis is needed. In this short paper we focus on the intra-NoC communication on a Tilera TILE64-like NoC. First, we extend the Recursive Calculus (RC) to achieve tighter intra-NoC WCTT. Then, we explain how this intra-NoC WCTT analysis could be used in a compositional manner for the end-to-end inter-NoC delay analysis.

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