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Analytical Performance Modeling and Validation of Intel's Xeon Phi Architecture
Author(s) -
Sudheer Chunduri,
Prasanna Balaprakash,
Vitali Morozov,
Venkatram Vishwanath,
Kalyan Kumaran
Publication year - 2017
Publication title -
osti oai (u.s. department of energy office of scientific and technical information)
Language(s) - English
Resource type - Conference proceedings
DOI - 10.1145/3075564.3075593
Subject(s) - xeon phi , computer science , xeon , code (set theory) , parallel computing , computer architecture , architecture , supercomputer , software , hardware architecture , embedded system , operating system , programming language , art , set (abstract data type) , visual arts
Modeling the performance of scientific applications on emerging hardware plays a central role in achieving extreme-scale computing goals. Analytical models that capture the interaction between applications and hardware characteristics are attractive because even a reasonably accurate model can be useful for performance tuning before the hardware is made available. In this paper, we develop a hardware model for Intel's second-generation Xeon Phi architecture code-named Knights Landing (KNL) for the SKOPE framework. We validate the KNL hardware model by projecting the performance of minibenchmarks and application kernels. The results show that our KNL model can project the performance with prediction errors of 10% to 20%. The hardware model also provides informative recommendations for code transformations and tuning.

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