Performance modelling of a multiprocessor bus architecture

This paper describes a discrete event simulation model of the bus architecture of a tightly coupled multiprocessor system. The newly announced multiprocessor system was being evaluated as a replacement for four old minicomputers with shared memory. The multiprocessor system was not yet available for benchmarking. Therefore, the models described here, along with other models, were used to estimate the performance of the multiprocessor system based on workload characterization of the old minicomputers that were being replaced. Two tools were used to build the simulation models. The performance models were first developed using the Performance Analysts Workbench System@ (PAWS@). The second modelling tool, Network IIS@, was subsequently used to model the same computer system as a part of an evaluation of that tool. A comparison of the models demonstrated the differences between the two tools.