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The most important precondition for top-down chip planning is a good area estimation. However, each estima- tion has tolerances which result in differences of the esti- mated shapes in thejloorplan and the final layouts. This paper introduces an improved top-down chip plan- ning method that reduces the effects of these deviations. In a fully recursive approach, each cell is planned several times with different presumptions. Bottom-up adjustment steps use refined shape functions instead of rigid dimen- sions. Although we perform such bottom-up adjustment steps, the general direction is top-down. The convergence of our procedure can be ensured. Within the paper, we describe our method in detail and provide some experimental results. Several real big test designs (the largest example has nearly 300.000 standard cells) have been performed with our PLAYOUT design system to compare the pure top-down approach with our new method.

Three-phase chip planning—an improved top-down chip planning strategy