Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis

Previous research into the problem of cell library synthesis for digital VLSI design has concentr ated mostly on rel- atively simple 1-dimensional cell topolo gies for static CMOS designs. Recent inter est has emerged in less constrained 2-dimensional topologies to support more complex non-dual circuits such as latches and flip flops, as well as high performance circuit families such as CVSL, PTL, and domino CMOS. W e discuss a CAD methodolo gy which supports a g eneralized placement,and routing approach to the realization of mask geometry for such comple x cir cuits. We explore the options available within this methodolo gy, show how the transistor level placement and routing problems at the transistor level differ from those at the block le vel, and present some results for a pr ototype tool, TEMPO, which adopts this methodology. CSE-TR-364-98: Transistor Level Micro Placement and Routing,1