Test generation for comprehensive testing of linear analog circuits using transient response sampling
Author(s) -
Pramodchandran N. Variyam,
Abhijit Chatterjee
Publication year - 1997
Publication title -
1997 proceedings of ieee international conference on computer aided design (iccad)
Language(s) - English
Resource type - Book series
SCImago Journal Rank - 0.501
H-Index - 88
ISSN - 1092-3152
ISBN - 0-8186-8200-0
DOI - 10.1145/266388.266512
The problem of testing analog components continues to be the bottleneck in reducing the time-to-market of mixed-signal ICs. In this paper, we present a test generation algorithm for implicit functional testing of linear analog circuits using transient response sampling. Each specification of the circuit under test (CUT) imposes bounds on individual parametric deviations under the single fault assumption. These bounds are mapped on to "acceptable" ranges of measurements of the transient response of the CUT at various sample points using time domain sensitivity calculations. Any circuit that "passes" the applied test is also guaranteed to meet its specifications. The simplicity of the test waveform, reduced test generation time and test time show that this testing method is a good alternative to existing testing schemes.
Accelerating Research
Robert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom
Address
John Eccles HouseRobert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom