Augmented partial reset

Diminishing the price of testing digital VLSI circuits is the goal of design for testability (DFT) techniques. Recently, a new approach called partial reset has been added to the suite of DFT techniques. Only a subset of the flip-flops are capable of resetting. This approach obtained reasonably high coverage. We show here that controllability is further enhanced by using multiple reset lines. The configuration of these multiple reset lines is described. This technique has been evaluated on the 1989 ISCAS sequential benchmark circuits and the results are discussed.