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A new on-chip test generation technique based on the built-in seg test (BIST) and deterministic test generation concepts has been proposed. Given a test set, the test patterns can be regenerated on the chip and applied to the circuit under test without the use of any external test equipments. A systematic procedure for the modification of a basic linear feedback shif’t register (LFSR) t o realize the on-chap test generation hardware as given. Since the delay introduced b y the modification of the LFSR is only two ga te delays, at-speed testing of circuits is feasible. Experiments are conducted and test application time and hardware overhead are compared with a known test technique under the same fault coverage conditions. It is shown lhat both test cost and test application time can be decreased significantly b y using the proposed technique.

On-chip test generation for combinational circuits by LFSR modification