Conflict modelling and instruction scheduling in code generation for in-house DSP cores

Application domain specific DSP cores ar e becoming increas- ingly popular due to their advantageous trade-off between flexibility and cost. However, existing code generation methods are hampered by the combination of tight timing and r esource constraints, imposed by the throughput requirements of DSP algorithms together with a fixed core architecture. In this paper, we present a method to model resource and instruction set conflicts uniformly and statically before scheduling. With the model we exploit the combination of all possible constraints, instead of being hampered by them. The approach results in an exact and run time efficient method to solve the instruction scheduling problem, which is illustrated by real life examples.