Open AccessA reconfigurable cache architecture for energy efficiency
Author(s) -
Karthik T. Sundararajan,
Timothy M. Jones,
Nigel Topham
Publication year - 2011
Publication title -
citeseer x (the pennsylvania state university)
Language(s) - English
Resource type - Conference proceedings
DOI - 10.1145/2016604.2016616
Subject(s) - cache , control reconfiguration , computer science , cache algorithms , cache coloring , cache invalidation , cache pollution , energy consumption , smart cache , embedded system , architecture , parallel computing , mesi protocol , workload , computer architecture , cpu cache , page cache , operating system , engineering , art , electrical engineering , visual arts
On-chip caches often consume a significant fraction of the total processor energy budget. Allowing adaptation to the running workload can significantly lower their energy consumption. In this paper, we present a novel Set and way Management cache Architecture for efficient Run-Time reconfiguration (Smart cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energy-delay of the Smart cache is on average 18% better than state-of-the-art reconfiguration architectures.
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